RISC-V is an open instruction set architecture, which is the interface between software and a processor. As an open standard it accelerates new innovative chip platforms, industry competition and easier access from academia.
The AEMY team is one of the key European entities of RISC-V and is involved in the RISC-V leadership and broad community. In research we focus on the extendability of RISC-V in the following areas:
- RISC-V compressed instructions for signal processing
- RISC-V support to accelerate the execution of bytecode virtual machines
- Framework for the exploration of RISC-V high-density compressed instructions using variable length instruction coding for application domains