We offer positions in our team for current and upcoming projects in the area of open source chip design tools.
Your tasks include:
- Exploration of data models for incremental formal verification
- Design and Implementation of a database for formal verification
- Integration and extension of verification algorithms with the database
- Collaboration on the Yosys open-source suite
You are the excellent candidate, if you fullfill the following requirements
- Completed Master’s degree in Computer Science, Electrical and Information Engineering, or comparable fields of study
- Basic understanding of digital circuit design, ideally with experience in verification
- Knowledge on formal methods in computer science
- Existing open source experience desirable